1. Field of the Invention
The present invention relates to a probe apparatus having a burn-in test function and capable of conducting burn-in tests on objects to be tested such as semiconductor chips on a semiconductor wafer and a circuit board of LCD and, more particularly, to a probe apparatus having a burn-in test function with a convey section for conveying the objects one by one. In addition, the present invention relates to a burn-in apparatus having a convey section for conveying the objects one by one.
2. Description of the Related Art
As the final steps of a semiconductor manufacturing process, a plurality of test steps are required. With tests in these test steps, the distribution of defective chips to users is prevented. A probe test is a typical test step of this type. In this probe test, a probe test apparatus is used. This apparatus has probes which are brought into contact with all the electrode pads of one chip of a large number of semiconductor chips on a semiconductor wafer. A signal pattern is supplied to each semiconductor chip by using the probe test apparatus, and an output from each chip is monitored, thereby testing the electrical characteristic of each semiconductor chip. In this probe test apparatus, in order to test all the chips on a semiconductor wafer, a wafer chuck on which the semiconductor wafer is held must be vertically moved and stepped by a distance corresponding to one chip every time a test on one chip is completed.
As the final steps of a semiconductor manufacturing process, a marking step and a repair step are performed in addition to a probe test step. In the marking step, a chip determined as a defective chip by the probe test is marked by using an ink or the like. In the repair step, a repairable defective chip is repaired. Furthermore, as a final test step, a visual test step is required, in which the semiconductor chips on a semiconductor wafer are magnified and visually observed.
There are proposed apparatuses for executing these test steps by an inline system.
The probe apparatus system disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2-265255 is one example of such apparatuses. This system comprises a linear convey path on which a wafer cassette is conveyed, a plurality of test sections and a repair section arranged on both or one side of the linear convey path, and a handler for supplying semiconductor wafers mounted in the cassette to the respective test sections and the repair section. This example will be referred to as the first system hereinafter.
Another example is disclosed in Jpn. Pat. Appln. KOKAI Publication No. 4-139851, which is a test apparatus comprising a linear convey path for conveying a semiconductor wafer, a plurality of test sections and a repair section arranged on both or one side of the linear convey path, and a convey means for conveying semiconductor wafers on the linear convey path one by one and supplying the semiconductor wafers to the respective test sections and the repair section. This example will be referred to as the second system hereinafter.
The above two systems are different from each other in the following point. In the first system, a cassette is conveyed, whereas in the second system, a semiconductor wafer is conveyed. Either system can be construed as a system equivalent to a cluster tool system disclosed in U.S. Pat. No. 5,292,393 Jpn. Pat. Appln. KOKAI Publication No. 3-192525 except that a convey means of a rotating convey system is replaced with a convey means of a linear convey system, and test sections and a repair section are arranged in place of a plurality of process chambers.
As a final test of a semiconductor manufacturing process, a burn-in test is conducted in addition to the above probe test. In this burn-in test, semiconductor chips are driven in a state similar to an actual driven state while temperature and/or voltage stresses are applied to the semiconductor chips, thereby finding semiconductor chips which are subjected to infant failures of semiconductor devices manufactured by using the chips. In these conventional systems, this burn-in test is not conducted on each semiconductor chip on a semiconductor wafer but is conducted on each semiconductor device obtained by cutting a semiconductor wafer into chips and packaging them.
The purpose of burn-in tests on semiconductor devices is to find devices having intrinsic defects and potential failures and remove the devices. Therefore, even if, for example, the type of a failure caused in a semiconductor device is identified, it is almost impossible to repair the device after packaging. For this reason, there is no choice but to discard semiconductor devices determined as defective devices by burn-in tests, resulting in a waste of time and money. Under the circumstances, there have been demands for burn-in tests on semiconductor chips on a semiconductor wafer.
The biggest problem in burn-in tests on semiconductor chips on a semiconductor wafer instead of semiconductor devices is that the time required for a burn-in test is longer than that required for a probe test.
Consider, for example, a 1-M DRAM as a semiconductor chip. In this case, signals must be sequentially supplied to 1,031 word lines. In addition, in order to find a failure in a gate oxide film due to a stress, the time required for a test per word line becomes considerably long. As a result, it takes about 31 hours to conduct a burn-in test on the overall 1-M DRAM as a chip.
Although this burn-in test time may be shortened by devising some wiring pattern, the following problems are posed in applying the above two inline systems to burn-in tests.
Consider, for example, a case wherein a burn-in test function is incorporated in the apparatus of the first system. In this case, the time taken for tests in one test section is equal to the time required to complete tests on all semiconductor wafers in a cassette loaded into the section. That is, until tests on a semiconductor wafer group (e.g., 25 wafers) as one lot in the test section are completed, non-processed and/or processed semiconductor wafers stored in a cassette cannot be supplied to the remaining test sections. Therefore, the remaining sections are kept in a standby/empty state. Even if another test section for conducting the same type of test is set in an empty state, non-processed semiconductor wafers stored in a cassette cannot be loaded into this test section in the empty state. Consequently, the overall operating efficiency of the apparatus decreases, and a high throughput cannot be expected.
Consider a case wherein a burn-in test function is incorporated in the apparatus of the second system. In this case, the above problem in the first system can be solved. That is, in the apparatus of the second system, since semiconductor wafers are conveyed one by one to be supplied to each test section or a repair section, processed wafers can be sequentially conveyed and supplied to the next test section or the repair section. In addition, when a specific test section is occupied, another identical test section in an empty state can be found, and a non-processed wafer can be conveyed and supplied to the section.
In the apparatus of the second system, however, probe test apparatuses or other test apparatuses as finished products are simply arranged on both or one side of a linear robot convey apparatus. For this reason, every time a semiconductor wafer is loaded into each test section or the repair section, the same operation, e.g., pre-alignment, must be repeatedly performed, resulting in a waste of time.